Can you combine the Verilog and SystemVerilog sections into one? It's a single language that evolved.
There is no Verilog any more, it's all SystemVerilog now (well, for 16 years now). What most tools support is a limited subset of the synthesizable part of SystemVerilog. Most of them at least support SystemVerilog-2005 (1800-2005), matching roughly the last "Verilog" standard.
It's the same with VHDL, where tools are more likely to support older versions of the VHDL standard, but not the latest additions.
There is no Verilog any more, it's all SystemVerilog now (well, for 16 years now). What most tools support is a limited subset of the synthesizable part of SystemVerilog. Most of them at least support SystemVerilog-2005 (1800-2005), matching roughly the last "Verilog" standard.
It's the same with VHDL, where tools are more likely to support older versions of the VHDL standard, but not the latest additions.
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I think this is a pretty silly thing to day. C is to Verilog as C++ is to SystemVerilog.
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I don't think this analogy holds. The C language is actively developed and releases new versions, the same way new C++ standard releases are made.
Verilog on the other hand doesn't release any updates any more, all improvements are in SystemVerilog.
Verilog on the other hand doesn't release any updates any more, all improvements are in SystemVerilog.
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You're suggesting
