A | B | C | D | E | F | G | H | I | J | K | L | M | N | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
1 | j.mp/si130nm-sizes | µm2 | x µm | y µm | x mm | y mm | mm2 | kcells | transistors (million) | source | ||||
2 | Microcontrollers | µm2 | x µm | y µm | x mm | y mm | mm2 | kcells | transistors | |||||
3 | Cypress cy8c4245axi - PSoC 4200 | 2120.00 | 3210.00 | 6.800 | https://siliconpr0n.org/archive/doku.php?id=azonenberg:cypress:cy8c4245axi | |||||||||
4 | PIC PIC32MZ2048ECH100 | 5800.00 | 5500.00 | 31.900 | https://siliconpr0n.org/archive/doku.php?id=azonenberg:microchip:pic32mz2048ech | |||||||||
5 | Duran mRISC, a RISC-V RV32IM core that consumes in 130nm | 0.120 | https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8106976 | |||||||||||
6 | CPU Cores | µm2 | x µm | y µm | x mm | y mm | mm2 | kcells | transistors | |||||
7 | ARM “minimum” Cortex-M0 | 0.072mm2 @ 50MHz | 0.072 | 7-track high density library at a utilization of placement density between 80-85% | ||||||||||
8 | ARM “minimum” Cortex-M0 typical configuration (including wakeup interrupt controller and debug access port) | 0.12mm2 @ 50MHz | 0.120 | 7-track high density library at a utilization of placement density between 80-85% | ||||||||||
9 | ARM “minimum” Cortex-M0 typical configuration (including wakeup interrupt controller and debug access port) | 0.25mm2 @ 100MHz. | 0.250 | 7-track high density library at a utilization of placement density between 80-85% | ||||||||||
10 | ||||||||||||||
11 | Big Processors | µm2 | x µm | y µm | x mm | y mm | mm2 | kcells | transistors | |||||
12 | IBM PowerPC 970 | 118.000 | 58.000 | https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1332597 | ||||||||||
13 | Intel Itanium2 Processor | 374.000 | 410.000 | https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1240968 | ||||||||||
14 | Intel PentiumB 4 Processor | 55.000 | https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1015065 | |||||||||||
15 | High Performance Components | µm2 | x µm | y µm | x mm | y mm | mm2 | kcells | transistors | |||||
16 | 5-GHz 32-bit integer execution core | 1.61 | 1.44 | 2.318 | 0.160 | https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1046084 | ||||||||
17 | 4-GHz Address Generation Unit With 32-bit Sparse-Tree Adder Core | https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1196212 | ||||||||||||
18 | 6-GHz 256 32 bit Leakage-Tolerant Register File | 31,684.00 | 89.00 | 356.00 | https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=997856 | |||||||||
19 | Flash Cells | µm2 | x µm | y µm | x mm | y mm | mm2 | kcells | transistors | |||||
20 | A Sub-1V-Read Flash Memory | Cell Size | 22.12 | 2.88 | 7.68 | https://ieeexplore.ieee.org/document/8351282 | ||||||||
21 | A Sub-1V-Read Flash Memory | System | 103,350.00 | 530.00 | 195.00 | 103.350 | https://ieeexplore.ieee.org/document/8351282 | |||||||
22 | ||||||||||||||
23 | SONOS (Silicon-Oxide-Nitride-Oxide-Silicon) cell | nvSRAM | https://www.cypress.com/file/214096/download | |||||||||||
24 | High Density Etox Flash | Flash Cell | 0.16 | https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=979398 | ||||||||||
25 | ||||||||||||||
26 | High Density Ferroelectric Memory Embedded | eFRAM | 0.58 | https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1175897 | ||||||||||
27 | High Density Ferroelectric Memory Embedded | SRAM? | 1.95 | https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1175897 | ||||||||||
28 | ||||||||||||||
29 | Embedded FRAM Utilizing | eFRAM | 0.54 | https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1278586 | ||||||||||
30 | Embedded FRAM Utilizing | eFRAM Capacitor | 0.25 | https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1278586 | ||||||||||
31 | ||||||||||||||
32 | Spin-Transfer Torque RAM | STT-RAM - 1T1J | 4.57 | https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6071019 | ||||||||||
33 | ||||||||||||||
34 | Spin-Transfer Torque RAM | 16 Kb STT-RAM | 0.540 | https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6071019 | ||||||||||
35 | Spin-Transfer Torque RAM | memory array size | 0.089 | https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6071019 | ||||||||||
36 | ||||||||||||||
37 | SRAM Cells - 6T-SRAM | µm2 | x µm | y µm | x mm | y mm | mm2 | kcells | transistors | |||||
38 | High Density | 6T-SRAM | 1.87 | https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=934971 | ||||||||||
39 | IBM PowerPC 970 | 6T-SRAM | 2.16 | https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1332597 | ||||||||||
40 | Infineon 130nm | 6T-SRAM | 2.28 | |||||||||||
41 | SilTerra’s CL130AL technology | SRAM? | 2.38 | |||||||||||
42 | Ultra High Density Standard Cell Logic Library Full, TSMC 130G HVt - SRAM - Dense SP | 6T-SRAM | 2.43 | |||||||||||
43 | SilTerra’s CL130G technology | SRAM? | 2.43 | |||||||||||
44 | High Speed | 6T-SRAM | 2.49 | https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=934971 | ||||||||||
45 | Intel Itanium2 Processor | SRAM? | 2.45 | https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1240968 | ||||||||||
46 | Random Measurement | 6T-SRAM | 2.91 | https://siliconpr0n.org/archive/doku.php?id=tech:start | ||||||||||
47 | SRAM Cells - 8T-SRAM | µm2 | x µm | y µm | x mm | y mm | mm2 | kcells | transistors | |||||
48 | Ultra High Density Standard Cell Logic Library Full, TSMC 130G HVt - Dense DP | 8T-SRAM | 5.75 | |||||||||||
49 | Transistor Sizing | µm2 | x µm | y µm | x mm | y mm | mm2 | kcells | transistors | |||||
50 | Rad Hardened on TSMC 130G | Transistor | 1.000 | 86 | ||||||||||
51 | Skywater - Gates with routing ? | scs8lsa - Low Voltage, Low Speed | 1.000 | 100 | ||||||||||
52 | sxlib (Alliance) | Transistor | 9.08 | 5.50 | 1.65 | 1.000 | 110 | @ 100% util | http://www.vlsitechnology.org/html/libraries03.html | |||||
53 | vxlib | Transistor | 9.08 | 5.50 | 1.65 | 1.000 | 110 | @ 100% util | http://www.vlsitechnology.org/html/libraries02.html | |||||
54 | rgalib | Transistor | 6.39 | 4.84 | 1.32 | 1.000 | 157 | @ 100% util | http://www.vlsitechnology.org/html/libraries02.html | |||||
55 | vgalib | Transistor | 6.39 | 4.84 | 1.32 | 1.000 | 157 | @ 100% util | http://www.vlsitechnology.org/html/libraries02.html | |||||
56 | Random Foundary | Transistor | 6.05 | 4.92 | 1.23 | 1.000 | 165 | |||||||
57 | wsclib | Transistor | 5.81 | 4.40 | 1.32 | 1.000 | 172 | @ 100% util | http://www.vlsitechnology.org/html/libraries02.html | |||||
58 | ST - 130nm HCMOS9GP | Transistor | 1.000 | 180 | ||||||||||
59 | vsclib | Transistor | 5.23 | 3.96 | 1.32 | 1.000 | 191 | @ 100% util | http://www.vlsitechnology.org/html/libraries02.html | |||||
60 | Infineon 130nm | Transistor | 1.000 | 204 | ||||||||||
61 | Skywater - Gates without routing ? | scs8lsa - Low Voltage, Low Speed | 1.000 | 209 | @ 100% util | |||||||||
62 | UMC | Transistor | 3.84 | 3.20 | 1.20 | 1.000 | 260 | |||||||
63 | µm2 | x µm | y µm | x mm | y mm | mm2 | kcells | transistors | ||||||
64 | Infineon 130nm | NAND Gates | 1.000 | 156 | ||||||||||
65 | GF 130nm | NAND Gates | 1.000 | 128 | ||||||||||
66 | GF 130nm | DFF | 1.000 | 24 | ||||||||||
67 | FPGA with Improved Routability and Robustness | 12T SRAM | 47 l | 64 l | 2.250 | https://arxiv.org/pdf/1712.03411.pdf | 64 configurable logic blocks (CLBs) that each contain a 6-input LUT | 12 custom macro-blocks with 26KB of programming SRAM | ||||||
68 | PHY Info | µm2 | x µm | y µm | x mm | y mm | mm2 | kcells | transistors | |||||
69 | ||||||||||||||
70 | ||||||||||||||
71 | ||||||||||||||
72 | ||||||||||||||
73 | ||||||||||||||
74 | Analog | µm2 | x µm | y µm | x mm | y mm | mm2 | kcells | transistors | |||||
75 | ADC - 12-bit SAR | 293,551.00 | 373.00 | 787.00 | 0.294 | |||||||||
76 | PLL | 237,684.04 | 541.73 | 438.75 | 0.238 | |||||||||
77 | POR | 5,580.00 | 90.00 | 62.00 | 0.006 | |||||||||
78 | ||||||||||||||
79 | Skywater 130nm | 1 Megabit SRAM | 2.000 | |||||||||||
80 | Global Foundaries 130nm | 1 Megabit Flash | 2.200 | |||||||||||
81 | ||||||||||||||
82 | ||||||||||||||
83 | ||||||||||||||
84 | ||||||||||||||
85 |